For more than five decades, the advancement of computing technology followed a consistent pattern: greater performance, smaller devices, and lower costs, all on a predictable timeline. 

This trajectory, famously captured by Moore’s Law, projected that computing elements on an integrated circuit would increase twofold approximately every couple of years, driving significant improvements in speed, efficiency, and cost per function. This eventually became the implicit benchmark for innovation across industries, from consumer electronics to aerospace, data centres to scientific research.

This pace of progress has shaped not only the performance of our devices but also the economic model underpinning the global tech ecosystem. As chips became more powerful and affordable, the benefits cascaded into everyday applications. Faster processors, energy-efficient sensors, and more capable smartphones were all direct outcomes of this scaling principle.

But today, the industry is approaching fundamental physical boundaries. What was once a reliable roadmap now presents diminishing returns, prompting a shift in strategy. Rather than continuing to scale silicon alone, the focus is moving toward integrating new materials and approaches—ushering in the era of photonics.

The Enduring Principle of Chip Advancement

In 1965, Gordon Moore made a simple observation: the number of transistors on an integrated circuit had been steadily increasing, and if that trend continued, it could double roughly every year. 

Over time, as fabrication capabilities matured and real-world data accumulated, the industry adjusted this timeline to roughly every 18 to 24 months. Despite these shifts, the exponential nature of the pattern held steady for decades, serving as a guiding reference for semiconductor development.

Importantly, Moore’s Law is not a scientific law in the formal sense. It does not describe a physical constant, nor is it derived from first principles. Rather, it reflects the industry’s sustained ability to improve chip performance and reduce cost through continuous innovation in design and manufacturing. Its influence extended far beyond the transistor count—it became a strategic benchmark used to set expectations across product planning, investment cycles, and technology roadmaps.

For years, this trajectory enabled a consistent cadence of advancement. Devices grew faster, more compact, and more accessible. At the heart of this progress was the steady evolution of semiconductor process technologies, which made room for denser circuitry and more complex architectures. 

This meant that Moore’s Law wasn’t just a prediction; instead, it acted as a powerful motivator that shaped how the industry approached innovation and scale.

Confronting Physical and Economic Barriers

But as transistors edge closer to atomic dimensions, the methods that once sustained decades of progress are now meeting resistance both physically and economically.

The Squeeze on Silicon Scaling

Shrinking transistor dimensions has long been the strategy for improving chip performance, but this approach is now nearing its physical threshold. 

At sub-nanometre scales, transistors begin to exhibit quantum mechanical behaviours, such as tunnelling, that interfere with stable operation. The smaller the features become, the harder it is to manage leakage current and thermal dissipation, both of which compromise power efficiency and reliability.

To navigate these constraints, semiconductor manufacturing has become significantly more complex. Producing advanced nodes now requires multiple patterning steps to replicate extremely fine features with precision. These techniques, while necessary, increase fabrication time, introduce more points of failure, and demand tighter integration across design and process teams. As a result, design cycles are longer, and yield management becomes increasingly difficult. The path forward remains open, but no longer linear.

Diminishing Returns on Investment

Pushing into smaller nodes has not only become technically demanding, but also economically unsustainable for many. In fact, according to the Boston Consulting Group (BCG), the cost of developing a modern system-on-chip can now exceed one billion dollars, especially when accounting for specialised processing blocks. As a result, for companies without the scale or resources to absorb such costs, the barriers to entry are growing.

Even when these investments are made, the returns are not what they used to be. 

Earlier nodes often brought substantial jumps in performance, efficiency, and transistor density. Today, those benefits are less dramatic. The gains remain, but they come slower, and at greater cost. This deceleration marks a fundamental shift in how the industry measures progress. 

This means that Moore’s Law, while still influencing roadmaps in valid ways, no longer delivers exponential results on its own. The focus now shifts to alternative technologies that can pick up where traditional scaling leaves off.

The Quantum Leap: Embracing Photonic Computing

With the limits of transistor scaling coming into sharper focus, the search for fundamentally different computing paradigms is no longer theoretical.

Rather, it has become essential. 

Photonic computing offers one such shift, trading electrons for light to unlock performance levels that silicon alone cannot reach.

Pivoting to Photonics

Unlike conventional systems that rely on the movement of electrons, photonic computing uses photons to process and transmit information.

This transition brings significant advantages. 

Photons travel at the speed of light, carry more data, and generate less heat compared to their electronic counterparts. These attributes allow for ultra-fast data throughput—a characteristic that aligns closely with the needs of emerging data-intensive workloads.

As computing demands escalate, especially in fields like artificial intelligence, telecommunications, and scientific modelling, photonic chips offer a path forward. Their ability to support high-speed parallelism and energy-efficient processing makes them especially relevant for next-generation applications where latency, power, and bandwidth constraints are critical.

This shift is already underway. The convergence of photonics and AI is laying the foundation for new modes of computation, where light not only moves data but plays an active role in logic and learning.

Advancing Interconnects with Integration

As chip architectures evolve, the bottleneck is no longer confined to logic—it extends to how fast and efficiently data can move between components. This is where photonic interconnects become essential. 

Optical waveguides enable high-bandwidth, low-latency data transmission within and between chips, replacing traditional copper traces that increasingly struggle with power loss and signal degradation at scale.

Co-packaged optics (CPO) has emerged as a compelling approach to address this challenge. 

By placing optical and electronic components side by side within the same package, CPO shortens channel lengths, lowers energy per bit, and improves signal integrity. This integration reduces the reliance on long copper connections and additional DSP stages that add latency and power draw.

The impact is particularly pronounced in data centre and high-performance computing environments, where demands for bandwidth density and energy efficiency continue to rise. Co-packaged optics not only supports higher throughput but also provides a scalable foundation for future network architectures. As integration techniques mature, CPO will play a central role in extending the performance roadmap beyond what conventional packaging allows, enabling faster, more efficient systems capable of meeting tomorrow’s compute demands.

NSTIC’s Catalytic Role in the Photonics Era